AIEDA Technology
AI for silicon teams, proven on silicon we build ourselves.
We build Ollie — an AI platform for semiconductor development — then use it to design, verify and physically implement a library of licensable IP. The platform is the product. The silicon is the proof.
- RTL → GDSIIThe whole flow, not a slice of it
- On your infrastructureAir-gapped if that is what it takes
- Your IP stays putOnly derived metadata ever moves
The problem
Expert attention is the bottleneck,
and it does not scale.
The people who can close timing on a hard block, judge whether a coverage hole matters, or explain why the energy regression appeared are the same people everything else is queued behind.
Design knowledge leaves with people
Why a block is built the way it is lives in a few heads and a decade of review comments. When they move on, the next team rediscovers it the expensive way.
A generic model does not know your design
It will produce confident SystemVerilog that ignores your clocking, your reset convention, and the reason that FIFO is depth six. Fluency is not familiarity.
Silicon review culture cannot absorb guesses
A tapeout schedule has no room for output nobody can trace. If a result cannot be reviewed the way RTL is reviewed, it cannot be used.
How we work
A standing team of domain specialists, not a chat window.
Named agents with defined roles — verification, physical design, timing, performance — that hold context across a programme and hand work between each other.
- Grounded in your design — agents answer against your RTL, your constraints and your results, inside your network.
- Sprint cadence — work is scoped and approved before it starts, and comes back with evidence attached.
- You hold the gate — nothing executes through a pending approval, and nothing interrupts you to ask for one.
Guardrails
Reviewable the way RTL is reviewable.
Silicon has a review culture for a reason. Work that cannot be traced, challenged and signed off does not belong in it — so every procedure is built to be.
- Declared envelopes — a procedure states what it may read, write and execute before it runs; reaching outside halts it.
- Fails closed — a violated guard stops and reports. It does not finish most of the job and leave you to find the rest.
- Independently verified — a separate pass re-checks the result, and a second agent then argues against it.
- Reviewable like RTL — kickoff and signoff gates, evidence attached, every step replayable months later.
rtl/noc/**, constraints/*.sdcout/sta/** scopedrtl/noc/rtr_arb.svCoverage
The whole flow, front to back.
Specialists across the disciplines a real programme needs — not one assistant claiming all of them at once.
RTL design & analysis
SystemVerilog authored, reviewed and explained against the actual design — not a generic model guessing at your conventions.
Verification & UVM
Testbench construction, coverage-gap triage, failure root-cause with waveform evidence attached.
Formal methods
Machine-checked proofs of datapath behaviour, where a simulation campaign would only sample.
Synthesis
Constraint authoring, QoR triage, and the loop back into RTL when the constraint is not the problem.
Physical design
Floorplan through CTS, routing and signoff. Full RTL-to-GDSII on real subsystems, not a flow diagram.
Timing closure
Path-level analysis that names the governing constraint rather than listing a thousand violations.
Power & performance
Energy regression root-cause, IPC and stall attribution, perf-per-task against a stated baseline.
Analog & mixed-signal
SPICE automation, custom layout support, parasitic extraction and AMS verification workflows.
DFT
Scan insertion, coverage analysis, and the methodology automation around them.
Lint, CDC & rules
House rules enforced as executable procedure, resolved at run time instead of restated at every review.
Interconnect & NoC
Programmable fabric design, per-cycle modelling, and visualisation over TLM or live RTL.
Specs that stay true
Micro-architecture specs generated from the RTL, DV and perf sources, so the document cannot drift from the design.
Proof
We use it to build our own silicon.
The hardest question about an AI platform for silicon is whether anyone has shipped anything real with it. Our answer is a sister company whose entire IP library was designed, verified and physically implemented on this platform.
Zen Semiconductor
A licensable IP library, built on Ollie.
Cores, fabric, accelerators and peripheral IP — designed, verified, physically implemented and formally verified using the same platform we deploy into your environment.
RISC-V, high-perf to min-energy
Datacenter-class wide out-of-order cores, configurable cores, and minimum-energy routing cores.
NoC & fabric processors
A programmable network-on-chip on the die, extended up, out and across the datacenter.
Inference & SoCs
Transformer and LLM inference acceleration, a digital modem SoC, and an ADAS sensor-fusion chiplet.
33+ block IP library
The unglamorous blocks a real SoC needs, held to the same standard as the headline ones.
Work delivered for other clients is covered by their agreements and is not described here. We will walk you through it under NDA.
Grounding
Why this is not a language model with a Verilog prompt.
The model is one component. What decides whether an answer is usable is everything assembled around it.
Design-state daemons
Live structure from your actual design injected into the agent’s context, so an answer is one shot against the real thing rather than a conversation spent reconstructing it.
Addressable facts with provenance
Modules, ports, parameters and connectivity become citable units of truth. The agent looks a fact up and shows you the line it came from.
Spec generated from source
Micro-architecture documentation generated from RTL, DV and performance data — and regenerated when they change.
Your tools, your flow
Works against the Synopsys, Cadence and Siemens flows you already run, and the open ones too.
Confidentiality
Your IP does not leave the building.
Most teams we talk to cannot send RTL to an external API, and with most tooling that is the end of the conversation. It is the start of ours.
Inside your network, air-gapped where required. Licensed and export-controlled material stays exactly where it is.
Where indexing is involved the source stays in place and only derived structure moves — never the IP itself.
Model-agnostic by design, including models running entirely on your own hardware. No external inference call need ever be made.
Engagement
Two ways in.
Bring us the block
Our team designs, verifies and physically implements it on the platform, working inside your environment and your review process. You own the result outright.
Bring the platform in-house
Deploy Ollie on your own infrastructure with the enablement to make your team productive on it — your designs, your flow, your people.
Bring us a block you would rather not do again.
The fastest way to judge this is on something real and annoying from your own backlog, inside your own boundary. We will show you the work and the audit trail behind it.
We reply from an engineer, not a sequence.